Millimeter-wave and Terahertz Integrated Circuits in Silicon Technologies: Challenges and Solutions

Hello, my name is Payam Heydari. I am a Professor
of Electrical Engineering at the University of California Irvine. This lecture gives a
brief overview of millimeter-wave and Terahertz integrated circuits in silicon technologies,
challenges, and solutions. There are a number of applications for the
emerging mm-wave and THz frequency band. Some of the applications are indicated in this
slide, including the automotive short-range and long-range radars, short-range Gb/s wireless
communication, passive and active imaging, and THz imaging and spectroscopy. The mm-wave and THz frequency band for wireless
communication enables very high data rate communications, and this high data rate communication
is inspired by the well-known Shannon Theory of Channel Capacity. Accordingly to the Shannon
Theory, the channel capacity, C, is directly proportional to the signal bandwidth and has
a logarithmic relationship with the signal-to-noise ratio. Now, the use of very high carrier frequency
(around mm-wave and THz frequency) makes it possible to increase the bandwidth while maintaining
the small fractional bandwidth. The small fractional bandwidth is really the bandwidth
normalized by the carrier frequency. So what it means here is that I can increase the bandwidth
and as a result, I can increase the maximum data rate, which makes it possible to send
and transmit multi-Gb/s data. At the same time, operation at very high frequencies means
that the passive devices including inductors and antennas, when they are designed on-chip,
their effective footprint will become smaller and smaller. Shown here are two examples in
which the left one shows a die microphotograph of a dipole antenna, each with effective length
of 740um, and with a spacing of only 820um. On the right is a 4-element phase array transmitter,
which was presented at ISSCC 2013. As you can see, if you look at the die microphotograph
of this chip, we can identify 4 slot loop antennas over a very small area of only 2.2mm
x 2.2mm. What it means here is that I can accommodate more antenna elements – I can
increase the radiation, I can increase the output power over only a small footprint of
chip area. Another application which one can think of
for mm-wave and THz is imaging. For example, the imaging application in the domain of passive
imaging, in which black body radiation radiated by materials can be detected a receiver, which
we call a passive receiver. For example, shown here is a schematic of a passive receiver
comprising an antenna, a power detector, and baseband amplifier and integrator. Previously,
this design or this block diagram could only be design in advanced technologies, but due
to technology scaling together with the invention of a number of cool techniques, we can design
on-chip passive imaging receivers. For example, shown here is a representation of a single-element
passive imaging receiver, where the heterodyne architecture has been used to design a 1-element
imaging receiver. Due to the simplicity, with a small change, we can increase this number
of elements and as a result, we can design a focal plane array architecture with many
imaging elements. The fact that the transistors are very small and the on-chip antenna (going
into higher frequencies) is very small, makes it very possible to design this focal plane
array with small chip area. One important question is “why is silicon
technology used/favorable for designing highly-sophisticated systems?” Shown on the right is a comparison
between different technologies in terms of their cutoff frequency with respect to the
gate length or effective channel length. As it appears here in this plot, as the gate
length gets smaller and smaller, the cutoff frequency of the silicon MOSFET transistor
gets increasingly closer to the maximum operation frequency of a compound semiconductor – in
this case an Indium Phosphide HEMT transistor. So what it means here is that some of the
applications that have been under the territory of compound semiconductors now can be used
in more common, commercial silicon processes. At the same time, we can basically design
sophisticated systems comprising many arrays of radiators and detectors on a single chip.
A very good representation of this multi-antenna element is a paper presented at ISSCC 2013,
in which the authors presented a highly complex 94-GHz, 4-element phase array transmitter/receiver
on a single chip, and as I mentioned, the fact that the transistors are getting smaller,
we can design very sophisticated multi-antenna element systems on a single die. Despite the fact that the mm-wave and THz
frequency provides us with a number of potential advantages, there are a number of challenges
that need to be addressed before these integrated circuits can be fully utilized. For example,
as we increase the frequency towards the maximum operation frequency, we cannot really design
very high amplifiers with small/low noise figures. Also, the maximum output power and
efficiency are not that high at very high frequencies. There is one important notion,
which is really governed by nature, and that is that the free space path loss is directly
proportional to the square value of the frequency. What it means here is that as I increase the
frequency, the maximum distance between the transmitter and receiver is decreases very
quickly with frequency. This means that some of the applications of very high frequencies
are only limited to short-range communication. If we wanted to increase the distance a little
bit, we have to basically boost the power by using many antenna elements. Also, an on-chip
antenna is a very interesting feature that can be added to the fully integrated system
– the transmitter/receiver for example, however its gain and radiation efficiency is not sufficient.
Finally, for signal sources designed on-chip at very high frequencies – the phase noise
might be high and the tuning range might not be very wide. There are a number of solutions that have
recently been presented that address the lack of amplification. For example, we can basically
design transistor/amplification stages such that we can basically bring the transistors
(or amplification stages) close to the border of their stability. By designing these amplifiers
very carefully, we can boost the gain of these amplifiers. Shown here is an example of a
3-stage power amplifier at 210-GHz presented at ISSCC 2013, in which the authors used the
so-called over-neutralization technique to boost the gain of each amplification stage
so as to achieve higher gain. As for the solutions to low antenna gain and
low radiation efficiency, one interesting idea that has been examined and can be implemented
in a silicon platform is the use of massive multi-antenna transmitters and receivers that
incorporate special power combining. What this special power combining does is by using
many antenna elements on chip and by transmitting the signals coherently, we can basically achieve
high output power by combining this output power, especially in free space, and as a
result, mitigate the insufficient antenna gain and power gain of the on-chip power amplifiers
and the on-chip antennas. An example of a 4-element I/Q transmitter/receiver is shown
here, which was presented at ISSCC 2013. Solutions to limited output power, once again,
suggest the use of an array of synchronized signal sources, where each signal source incorporates
harmonic generation and multiplication circuits in order to boost the frequency. Then by using
these harmonic generators and by synchronizing these harmonic generators on chip, we are
able to increase the maximum output power. An example of this technique is shown here
where 16-element resonators and radiators have been designed and synchronized together
to achieve very high output power. A paper based on this idea was presented at ISSCC
2014. Finally, as I mentioned, the tuning range
and the phase noise might not be good enough at very high frequencies. One suggestion is
to use the closed-loop signal sources or based on phase-locked loops to lower the phase noise,
particularly the phase noise close to the center frequency, which we call close-in phase
noise, and increase the tuning range. In designing this closed-loop frequency synthesizer, if
we can co-design and co-optimize critical high-speed building blocks together, then
we can further optimize the performance. An example based on this co-designing and co-optimizing
of this high frequency element is shown here, where this frequency synthesizer operating
at 300-GHz based on the phase-locking technique was presented at ISSCC 2014. In summary, the vastly underutilized spectrum
in the sub-THz band enables a number of disruptive applications, such as 10+ Gb/s chip-to-chip
wireless communication, imaging, and spectroscopy. Owing to aggressive technology scaling of
both feature size and the operation frequency, the nanoscale silicon process might be a good
platform for designing very high frequency sophisticated systems, such as arrays of detectors
and radiators, phase arrays, massive MIMO transmitters and receivers with massive number
of elements. The high-frequency requirement imposes a number of challenges, both for the
architecture and circuit design at very high frequencies. In this talk, I provided an overview
of some of the challenges and some directions that hopefully solve some of these challenging
problems at very high frequencies. Thank you.

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